This application is related to patent application U.S. Ser. No. 14/252,464 filed on Apr. 14, 2014, as “Method of Fabricating an Integrated Circuit with Optimized Pattern Density Uniformity,” and U.S. Ser. No. 14/253,282 filed on Apr. 15, 2014, as “Method of Fabricating an Integrated Circuit with Block Dummy for Optimized Pattern Density Uniformity,” the entire disclosures of which are hereby incorporated by reference.
In integrated circuit (IC) manufacture, it is common to utilize optical proximity correction (OPC) to improve an imaging resolution of an IC pattern during a lithography patterning process. However, along with the progress of semiconductor technology, the feature sizes are continually getting smaller. The existing OPC methods to add various dummy features have a limited degree of freedom and effectiveness to tune the pattern density and poor uniformity of the pattern density. This presents issues such as dynamic space charge effect and micro-loading effect when an electron-beam lithography technology is used to form the IC pattern. Furthermore, during the process to insert dummy features, various simulations and calculations associated with the dummy features take more time, causing an increase in cost. Therefore, what is needed is a method for IC design and mask making to effectively and efficiently adjusting an IC pattern to address the above issues.